Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity

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概要

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• One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique for automatic test equipment applications. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.

• （社）電子情報通信学会の論文
• 2009-02-01

著者

• Asami Koji

  Advantest Corp. Gunma‐ken Jpn

• Asami Koji

  Advantest Corporation

• SUZUKI Takahide

  Electronic Engineering Department, Graduate School of Engineering, Gunma University

• MIYAJIMA Hiroyuki

  Electronic Engineering Department, Graduate School of Engineering, Gunma University

• TAURA Tetsuya

  Electronic Engineering Department, Graduate School of Engineering, Gunma University

• KOBAYASHI Haruo

  Electronic Engineering Department, Graduate School of Engineering, Gunma University

• Kobayashi Haruo

  Electronic Engineering Department Graduate School Of Engineering Gunma University

• Suzuki Takahide

  Electronic Engineering Department Graduate School Of Engineering Gunma University

• Taura Tetsuya

  Electronic Engineering Department Graduate School Of Engineering Gunma University

• Miyajima Hiroyuki

  Electronic Engineering Department Graduate School Of Engineering Gunma University

• ASAMI Koji

  ADVANTEST Corp.

関連論文

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• Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity
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• Analysis of CMOS ADC Nonlinear Input Capacitance
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• THD Measurement and Compensation for Analog Circuits with Fine CMOS Devices
• Total Harmonic Distortion Measurement System of Electronic Devices up to 100MHz with Remarkable Sensitivity
• Algorithms for Digital Correction of ADC Nonlinearity
• High-Speed Continuous-Time Subsampling Bandpass ΔΣAD Modulator Architecture Employing Radio Frequency DAC(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• Design of Fourth-Order Continuous-Time Bandpass ΔΣAD Modulator for RF Sampling
• Production Test Considerations for Mixed-signal IC with Background Calibration
• SAR ADC Architecture with Digital Error Correction
• Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths(AD/DA, Analog Circuit and Device Technologies)
• FOREWORD

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