A Reference Voltage Buffer with Settling Boost Technique for a 12bit 18MHz Multibit/Stage Pipelined A/D Converter
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概要
- 論文の詳細を見る
A reference voltage buffer for a multibit/stage pipelined ADC is described, where a settling boost technique is used to improve the settling response of the pipelined stages. A 12bit 18MHz pipelined ADC with the buffer is designed and simulated based on a 0.35µm CMOS process. According to simulation results, the power consumed by the reference voltage buffer is reduced by 33% compared to that without the settling boost technique.
- （社）電子情報通信学会の論文
- 2009-02-01
著者
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OKURA Tetsuro
The Division of Electrical, Electronic and Information Engineering, Osaka University
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Ido Toru
The Division Of Electrical Electronic And Information Engineering Osaka University
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Okura Tetsuro
The Division Of Electrical Electronic And Information Engineering Osaka University
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Okura Shunsuke
The Division Of Electrical Electronic And Information Engineering Osaka University
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OKURA Shunsuke
Division of Electrical, Electronic and Information Engineering, Osaka University
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OKURA Tetsuro
Division of Electrical, Electronic and Information Engineering, Osaka University
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TANIGUCHI Kenji
Division of Electrical, Electronic and Information Engineering, Osaka University
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Taniguchi Kenji
Division Of Electrical Electronics And Information Engineering Graduate School Of Engineering Osaka
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Taniguchi Kenji
The Division Of Electrical Electronic And Information Engineering Osaka University
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IDO Toru
Division of Electrical, Electronic and Information Engineering, Osaka University
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Taniguchi Kenji
Division Of Electrical Electronic And Information Engineering Osaka University
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Ido Toru
Division Of Electrical Electronic And Information Engineering Osaka University
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Taniguchi Kenji
Osaka Univ. Suita‐shi Jpn
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Okura Shunsuke
Division Of Electrical Electronic And Information Engineering Osaka University
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