Optimization of Layout and Doping Profile Design for BT(Body Tied)-FinFET DRAM
スポンサーリンク
概要
- 論文の詳細を見る
- 2005-09-13
著者
-
PARK Donggun
Device Research Team, R&D Center, Samsung Electronics Co.
-
Park Seung
Device Research Team R&d Center Samsung Electronics
-
Park Donggun
Device Research Team
-
LEE Chul
Device Research Team, Semiconductor R&D Center, Samsung Electronics
-
KIM Keunnam
Device Research Team, Semiconductor R&D Center, Samsung Electronics
-
KIM Keunnam
Advanced Technology Development Team
-
LEE Chul
Advanced Technology Development Team
-
PARK Donggun
Advanced Technology Development Team
-
LEE Choong-Ho
Device Research Team, R&D Center, Samsung Electronics
-
YOON Jae-man
Device Research Team, R&D Center, Samsung Electronics
-
KANG Hee
Device Research Team, R&D Center, Samsung Electronics
-
AHN Young
Device Research Team, R&D Center, Samsung Electronics
-
Lee Choong-ho
Device Research Team R&d Center Samsung Electronics
-
Yoon Jae-man
Device Research Team R&d Center Samsung Electronics
-
Ahn Young
Device Research Team R&d Center Samsung Electronics
-
Kang Hee
Device Research Team R&d Center Samsung Electronics
関連論文
- A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology
- Investigation on the Body Bias Dependency of Gate Induced Drain Leakage Current in the Body-Tied finFET
- RC-FinFET (Recessed Channel FinFET) Cell Transistor Technology for Future Generation DRAMs
- Optimization of Layout and Doping Profile Design for BT(Body Tied)-FinFET DRAM
- FinFET NAND Flash with Nitride/Si Nanocrystal/Nitride Hybrid Trap Layer
- A Comprehensive Study of Hot-Carrier Effects in Body-Tied FinFETs
- A Comprehensive Study of Hot-Carrier Behaviors with Consideration of Non-Local, Series Resistance, Quantum, and Temperature Effects in Multi-Gate FinFETs
- A Novel Multifin Dynamic Random Access Memory Periphery Transistor Technology Using a Spacer Patterning through Gate Polycrystalline Silicon Technique
- Nano Bowls of Carbon by Oxidative Chopping of Carbon Nano Sphere
- Fin-Type Field-Effect Transistor NAND Flash with Nitride/Silicon Nanocrystal/Nitride Hybrid Trap Layer
- Investigation of Body Bias Dependence of Gate-Induced Drain Leakage Current for Body-Tied Fin Field Effect Transistor
- Highly Manufacturable and Reliable 80-nm Gate Twin Silicon–Oxide–Nitride–Oxide–Silicon Memory Transistor
- Recessed Channel Fin Field-Effect Transistor Cell Technology for Future-Generation Dynamic Random Access Memories
- Three Series-Connected Transistor Model for a Recess-Channel-Array Transistor and Improvement of Electrical Characteristics by a Bottom Fin Structure