Fin-Type Field-Effect Transistor NAND Flash with Nitride/Silicon Nanocrystal/Nitride Hybrid Trap Layer
スポンサーリンク
概要
- 論文の詳細を見る
The effects of trap layer on NAND flash performances have been described in this paper. In order to overcome the slower programming speed of the discrete trap memory than conventional floating-gate device, nitride and silicon nanocrystal have been assembled together so as to provide the higher trap density for the improved device performance. This hybrid trap layer technology has been applied to the fin-type field-effect transistor (FinFET) NAND flash, and the results show ${\sim}5$ V of program/erase window with reasonable device reliabilities.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2007-04-30
著者
-
Sung Suk
Device Research Team
-
Park Donggun
Device Research Team
-
Choi Byoung
Device Research Team
-
CHOE Jeong-Dong
Device Research Team
-
LEE Se-Hoon
Device Research Team
-
LEE Jong
Device Research Team
-
CHO Eun
Device Research Team
-
AHN Youngjoon
Device Research Team
-
PARK Kyucharn
Device Research Team
-
Lee Se-Hoon
Device Research Team, Semiconductor R&D Center, Samsung Electronics Co., San #24, Nongseo-Dong, Giheung-Gu, Youngin-City, Gyeonggi-Do 449-711, Korea
-
Choi Byoung
Device Research Team, Semiconductor R&D Center, Samsung Electronics Co., San #24, Nongseo-Dong, Giheung-Gu, Youngin-City, Gyeonggi-Do 449-711, Korea
-
Chung Ilsub
School of Info rolation and Communications Engineering, Sun gKyunKwan University
-
No Jintae
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co., San #24, Nongseo-Dong, Giheung-Gu, Youngin-City, Gyeonggi-Do 449-711, Korea
-
Lee Jong
Device Research Team, Semiconductor R&D Center, Samsung Electronics Co., San #24, Nongseo-Dong, Giheung-Gu, Youngin-City, Gyeonggi-Do 449-711, Korea
-
Cho Eun
Device Research Team, Semiconductor R&D Center, Samsung Electronics Co., San #24, Nongseo-Dong, Giheung-Gu, Youngin-City, Gyeonggi-Do 449-711, Korea
-
Park Donggun
Device Research Team, Semiconductor R&D Center, Samsung Electronics Co., San #24, Nongseo-Dong, Giheung-Gu, Youngin-City, Gyeonggi-Do 449-711, Korea
-
Choe Jeong-Dong
Device Research Team, Semiconductor R&D Center, Samsung Electronics Co., San #24, Nongseo-Dong, Giheung-Gu, Youngin-City, Gyeonggi-Do 449-711, Korea
-
Chung Ilsub
School of Information and Communication Engineering, Sungkyunkwan University, Gyeonggi-Do 440-746, Korea
関連論文
- A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology
- Investigation on the Body Bias Dependency of Gate Induced Drain Leakage Current in the Body-Tied finFET
- Optimization of Layout and Doping Profile Design for BT(Body Tied)-FinFET DRAM
- FinFET NAND Flash with Nitride/Si Nanocrystal/Nitride Hybrid Trap Layer
- Application of Scanning Probe Microscope for Novel Characterization of Ferroelectric Capacitor
- Ferroelectric Properties of Very Thin Pb(Zr_Ti_)O_3 Film Determined by Kelvin Force Microscope
- A Comprehensive Study of Hot-Carrier Effects in Body-Tied FinFETs
- A Comprehensive Study of Hot-Carrier Behaviors with Consideration of Non-Local, Series Resistance, Quantum, and Temperature Effects in Multi-Gate FinFETs
- Evaluation of Aluminum Oxide Thin Film in Magnetic Tunneling Junction Utilizing Scanning Probe Microscopy
- Study On Charge Trap Layers In Charge Trap Metal–Oxide–Semiconductor Field Effect Transistor
- Fin-Type Field-Effect Transistor NAND Flash with Nitride/Silicon Nanocrystal/Nitride Hybrid Trap Layer
- Highly Manufacturable and Reliable 80-nm Gate Twin Silicon–Oxide–Nitride–Oxide–Silicon Memory Transistor
- Electrical Characterization of Sub-micron Magnetic Tunneling Junction Cells Using Scanning Probe Microscopy
- Study on Polarization Properties of Randomly Oriented Bi3.35La0.85Ti3O12 Ferroelectric Thin Film Utilizing Three-Dimensional Piezoresponse Image