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ULSI Research Laboratories, Toshiba Corporation | 論文
- Contamination Charging up Effect in a Variably Shaped Electron Beam Writer
- Electron Beam Calibration Method for Character Projection Exposure System EX-8D
- Evaluation of Shaping Gain Adjustment Accuracy Using Atomic Force Microscope in Variably Shaped Electron-Beam Writing Systems
- Optimization of a High-Performance Chemically Amplified Positive Resist for Electron-Beam Lithography
- Hiding Data Cache Latency with Load Address prediction
- Formation of Single-Crystal Al Interconnection by In Situ Annealing
- Inlaid Cu Interconnects Employing Ti-Si-N Barrier Metal for ULSI Applications
- Coulomb Blockade Effects in Edge Quantum Wire SOI MOSFETs
- Silicon-Based Single-Electron-Tunneling Transistor Operated at 4.2 K
- Evidence for Asymmetrical Hydrogen Profile in Thin D_2O Oxidized SiO_2 by SIMS and Modified TDS
- Three-Terminal Silicon Esaki Tunneling Device
- A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs (Special Issue on Low-Power LSI Technologies)
- Significant Effect of OH inside Silicon Chemical Oxides on AHF(Anhydrous Hydrofluoric Acid) Etching
- An Improved Bandgap Narrowing Model Based on Corrected Intrinsic Carrier Concentration
- KrF Excimer Laser Projection Lithography: 0.35μm Minimum Space VLSI Pattern Fabrication by a Tri-Level Resist Process
- Low-Power On-Chip Supply Voltage Conversion Scheme for Ultrahigh-Density DRAM's (Special Section on the 1992 VLSI Circuits Symposium)
- Large-Area Optical Proximity Correction with a Combination of Rule-Based and Simulation-Based Methods
- A High Performance 0.15μm Single Gate CMOS Technology
- Double-Level Cu Inlaid Interconnects with Simultaneously Filled Via-Plugs
- Double-Level Cu Inlaid Interconnects with Simultaneously Filled Via Plugs