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ULSI Laboratory, Mitsubishi Electric Corporation | 論文
- SiO_2 Etching Characteristics with Low-Energy Ions Generated by Electron Cyclotron Resonance Plasma Using CF_4 and NF_3 Gases
- High Performance Electron Cyclotron Resonance Plasma Etching with Control of Magnetic Field Gradient : Etching
- High Performance Electron Cyclotron Resonance Plasma Etching with Control of Magnetic Field Gradient
- Highly Selective AlSiCu Etching Using BBr_3 Mixed-Gas Plasma : Etching and Deposition Technology
- ECR Plasma Etching with Heavy Halogen Ions : Etching and Deposition Technology
- Direct Measurement of Transient Drain Currents in Partially-Depleted SOI N-Channel MOSFETs Using a Nuclear Microprobe for Highly Reliable Device Designs
- A Sub 1-V L-Band Low Noise Amplifier SOI CMOS(Special Section on Analog Circuit Techniques and Related Topics)
- A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
- Analyses of the Radiation-Caused Characteristics Change in SOI MOSFETs Using Field Shield Isolation
- Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)
- The Influence of the Buried Oxide Defects on the Gate Oxide Reliability and Drain Leakage Currents of the Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
- Suppression of Parasitic MOSFETs at LOCOS Edge Region in Partially Depleted SOI MOSFETs
- Analysis of the Delay Distributions of 0.5μm SOI LSIs (Special Issue on SOI Devices and Their Process Technologies)
- Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)
- Comparison of Standard and Low-Dose Separation-by-Implanted-Oxygen Substrates for 0.15 μm SOI MOSFET Applications
- High-Speed SOI 1/8 Frequency Divider Using Field-Shield Body-Fixed Structure
- Comparison of Standard and Low-Dose SIMOX Substrates for 0.15μm SOI MOSFET Applications
- Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect
- Two-Dimensional Analytical Modeling of the Source/Drain Engineering Influemce on Short-Channel Effects in SOI MOSFET's
- Analytical Modeling of Short-Channel Behavior of Accumulation-Mode Transistors on Silicon-on-Insulator Substrate