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The Ulsi Development Center Mitsubishi Electric Corporation | 論文
- Channel Characteristics and Performance of MIMO E-SDM Systems in an Indoor Time-Varying Fading Environment
- Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application(Special Issue on Integrated Systems with New Concepts)
- Direct Measurement of Transient Drain Currents in Partially-Depleted SOI N-Channel MOSFETs Using a Nuclear Microprobe for Highly Reliable Device Designs
- A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
- Analyses of the Radiation-Caused Characteristics Change in SOI MOSFETs Using Field Shield Isolation
- Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM (Special Issue on Ultra-High-Speed IC and LSI Technology)
- The Influence of the Buried Oxide Defects on the Gate Oxide Reliability and Drain Leakage Currents of the Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
- Analysis of the Delay Distributions of 0.5μm SOI LSIs (Special Issue on SOI Devices and Their Process Technologies)
- Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)
- Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect
- Analytical Modeling of Short-Channel Behavior of Accumulation-Mode Transistors on Silicon-on-Insulator Substrate
- A Spatial Domain Interference Canceller Using a Multistage Adaptive Array with Precise Timing Estimation (Special Issue on Adaptive Array Antenna Techniques for Advanced Wireless Communications)
- Combining Techniques for Spatial-Domain Path-Diversity Using an Adaptive Array
- A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)
- Control of Carrier Collection Efficiency in n^+p Diode with Retrograde Well and Epitaxial Layers
- Well Structure by High-Energy Boron Implantation for Soft-Error Reduction in Dynamic Random Access Memories (DRAMs)
- Estimation of Carrier Suppression by High-Energy Boron-Implanted Layer for Soft Error Reduction
- Disk-Shaped Stacked Capacitor Cell for 256 Mb Dynamic Random-Access Memory
- Soft-Error Study of DRAMs with Retrograde Well Structure by New Evaluation Method (Special Issue on Quarter Micron Si Device and Process Technologies)
- A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme