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Semiconductor Technology Academic Research Center | 論文
- Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG
- 100 nm-MOSFET Model for Circuit Simulation : Challenges and Solutions
- Approaches to Reducing Digital-Noise Coupling in CMOS Mixed-Signal LSIs (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
- Substrate Noise Reduction Using Active Guard Band Filters in Mixed-Signal Integrated Circuits (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
- Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90nm Technology and Beyond (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
- SoC Architecture Synthesis Methodology Based on High-Level IPs(System Level Design)(VLSI Design and CAD Algorithms)
- A Partial Scan Design Approach based on Register-Transfer Level Testability Analysis (Special Issue on Synthesis and Verification of Hardware Design)
- Gate Delay Estimation in STA under Dynamic Power Supply Noise
- Advanced Process/Device Modeling and Its Ompact on the CMOS Design Solution (Special lssue on SISPAD'99)
- Misleading energy and performance claims in sub/near threshold digital systems (集積回路)
- Surface-Potential-Based MOS-Varactor Model for RF Applications
- Enhanced Quantum Effect for Sub-0.1μm Pocket Technologies and Its Relevance for the On-Current Condition
- Frequency Dependence of Measured MOSFET Distortion Characteristic
- A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling (Special Section on Analog Circuit Techniques and Related Topics)
- Floating Gate Memory with Biomineralized Nanodots Embedded in High-$k$ Gate Dielectric
- A Statistical Quality Model for Delay Testing (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
- Nucleation and Growth Control of Al-CVD for Dual-Damascene Application
- Evaluation of Strain in Si-on-Insulator Substrate Induced by Si3N4 Capping Film
- Unified Reaction--Diffusion Model for Accurate Prediction of Negative Bias Temperature Instability Effect
- A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme