SoC Architecture Synthesis Methodology Based on High-Level IPs(System Level Design)(<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• We propose a sophisticated synthesis methodology for SoC (System-on-Chip) architectures from the system level specification based on reusable high-level IPs named as Virtual Cores (VCores), in this paper. This synthesis methodology generates an initial architecture that consists of a CPU, buses, IPs, peripherals, I/Os and an RTOS (Real Time Operating System), as well as making tradeoffs to the architecture, between hardware and software on assigned software VCores and hardware VCores. The results of an architecture level design experiment, using the proposed methodology, shows that the partial automation of the architecture synthesis process, allied with design reuse, accelerates the architecture design, therefore, reducing the time required to design an architecture of SoC.

• 2004-12-01

著者

• Nishi Hiroaki

  Semiconductor Technology Academic Research Center

• MURAOKA Michiaki

  Semiconductor Technology Academic Research Center

• MORIZAWA Rafael

  Semiconductor Technology Academic Research Center

• YOKOT Hideaki

  Semiconductor Technology Academic Research Center

• ONISHI Yoichi

  Semiconductor Technology Academic Research Center

• Muraoka Michiaki

  Semiconductor Technology Academic Research Center:(present Address)semiconductor Industry Research I

• Muraoka Michiaki

  Semiconductor Research Center Matsushita Electric Industrial Co. Ltd.

関連論文

• SoC Architecture Synthesis Methodology Based on High-Level IPs(System Level Design)(VLSI Design and CAD Algorithms)
• A Partial Scan Design Approach based on Register-Transfer Level Testability Analysis (Special Issue on Synthesis and Verification of Hardware Design)

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