スポンサーリンク
School Of Electrical Engineering And Computer Science Kyungpook National Univ. | 論文
- 2-bit/cell Characteristics of High-Density and High-Performance SONOS Flash Memory Cell with Recessed Channel Structure
- Device Design Consideration for 50nm Dynamic Random Access Memory Using Bulk FinFET
- Threshold Voltage Behavior of Body-Tied FinFET (OMEGA MOSFET) with Respect to Ion Implantation Conditions
- Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure
- Analytic oxide capacitance model of double- and surrounding-gate metal-oxide-semiconductor field-effect transistors in linear region by considering inversion-layer capacitance
- Isotropic/Anisotropic Selective Epitaxial Growth of Si on Local Oxidation of Silicon (LOCOS) Patterned Si (100) Substrate by Cold Wall Ultrahigh Vacuum Chemical Vapor Deposition (UHV-CVD)
- [Invited]Double-Gate MOSFETs for Nano CMOS Technology : Body-tied Double-Gate MOSFETs(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
- [Invited] Double-Gate MOSFETs for Nano CMOS Technology : Body-tied Double-Gate MOSFETs (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Gate Workfunction Engineering of Bulk FinFETs for Sub-50nm DRAM Cell Transistors
- Negative Bias Temperature Instability of Bulk Fin Field Effect Transistor
- Flash Memory Device with ‘I’ Shape Floating Gate for Sub-70 nm NAND Flash Memory
- Design of Bulk Fin-Type Field-Effect Transistor Considering Gate Work-Function
- Current Model of Fully Depleted Nanoscale Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel in All Operation Regions
- Threshold-Voltage Modeling of Bulk Fin Field Transistors by Considering Surface Potential Lowering
- Device Design Consideration for 50 nm Dynamic Random Access Memory Using Bulk FinFET
- Threshold Voltage Modeling of Fully Depleted Nanoscale Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel by Considering Drain Bias
- Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions
- Band-to-Band Hot-hole Erase Characteristics of 2-Bit/cell NOR-type Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory Cell with Spacer-type Storage Node on Recessed Channel Structure
- Two-Bit/Cell Programming Characteristics of High-Density NOR-Type Flash Memory Device with Recessed Channel Structure and Spacer-Type Nitride Layer
- Length Effect of Spacer-Type Storage Node in High-Density 2-bit/Cell Silicon–Oxide–Nitride–Oxide–Silicon NOR Flash Cell Based on Recessed Channel Structure