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Central Research Lab. Hitachi Ltd. | 論文
- Fabrication of 0.1μm Complementary Metal-Oxide-Semiconductor Devices : Micro/nanofabrication and Devices
- Fabrication of 0.1μm Complementary Metal-Oxide-Semiconductor Devices
- Fully Strained Heavily Carbon-Doped GaAs Grown by Gas-Source Molecular Beam Epitaxy Using Carbontetrabromide and Its Application to InGaP/GaAs Heterojunction Bipolar Transistors
- A WSi Base Electrode and a Heavily-Doped Thin Base Layer for High-Speed and Low-Power InGaP/GaAs HBTs
- Fully Strained Heavily Carbon-Doped GaAs Using Carbontetrabromide by Gas-Source Molecular Beam Epitaxy and Its Application in InGaP/GaAs Heterojunction Bipolar Transistors
- New Technologies of a WSi Base Electrode and a Heavily-Doped Thin Base Layer for High-Performance InGaP/GaAs HBTs
- A High-Endurance Read/Write Scheme for Half-V_cc Plate Nonvolatile DRAMs with Ferroelectric Capacitors(Special Issue on Nonvolatile Memories)
- Amorphous Channel SESO Memory with Good Logic Process Compatibility for Low-power High-density Embedded RAM
- Shallow p-Type Layers in Si by Rapid Vapor-Phase Doping for High-Speed Bipolar and MOS Applications (Special Issue on Ultra-High-Speed LSIs)
- High-Reliability Programming Method Suitable for Flash Memories of More Than 256Mb
- Long-Retention-Time, High-Speed DRAM Array with 12-F^2 Twin Cell for Sub 1-V Operation(Memory,Low-Power, High-Speed LSIs and Related Technologies)
- Dynamic Terminations for Low-Power High-Speed Chip Interconnection in Portable Equipment
- Behavior of Active and Inactive Boron in Si Produced by Vapor-Phase Doping during Subsequent Hydrogen Annealing
- Subquarter-Micrometer PMOSFET's with 50-nm Source and Drain Formed by Rapid Vapor-Phase Doping (RVD) (Special Issue on Quarter Micron Si Device and Process Technologies)
- PGMA as a High Resolution, High Sensitivity Negative Electron Beam Resist
- The Umbrella Cell : A High-Density 2T Cell for SOC Applications(Memory, Low-Power LSI and Low-Power IP)
- FOREWORD (Special Issue on ULSI Memory Technology)
- Sub 1V Swing Internal Bus Architecture for Future Low-Power ULSI's (Special Section on the 1992 VLSI Circuits Symposium)
- A Robust Array Architecture for a Capacitorless MISS Tunnel-Diode Memory(Integrated Electronics)
- The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips