Yamakawa Satoshi | Advanced Technology R&D Center, Mitsubishi Electric Corporation, 8-1-1 Tsukaguchi-Honmachi, Amagasaki, Hyogo 661-8661, Japan

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著作論文

Parasitic Resistance Reduction in Deep Submicron Dual-Gate Transistors with Partially Elevated Source/Drain Extension Regions Fabricated by Complementary Metal-Oxide-Semiconductor Technologies
Si Deposition into Fine Contact Holes by Ultrahigh-Vacuum Chemical Vapor Deposition
Effects of Eddy Current on Characteristics of Spiral Inductors on Silicon
Characteristics of Transmission Lines on Silicon-on-Metal and Silicon-on-Quartz
An Electrostatic-Discharge (ESD) Protection Device with Low Parasitic Capacitance Utilizing a Depletion-Layer-Extended Transistor (DET) for RF CMOS ICs
Pattern Density Effect on Characteristics of Spiral Inductor with Patterned Ground Shield
Si Deposition into Fine Contact Holes by Ultrahigh-Vacuum Chemical Vapor Deposition

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