Layout Dependent Induced Leakage and its Prevention with Different Shallow Trench Isolation Schemes in 0.18 μm Dual Gate Complementary Metal Oxide Semiconductor Technology

概要

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In this paper, an extreme leakage current at the narrowest isolation space between wide active patterns is found to cause severe yield damage and its mechanism and prevention method is investigated in 0.18 μm node high voltage technology. The narrowest isolation space neighboring to wide isolation space becomes much more narrowed in photoresist (PR) masked silicon (Si) trench etch by the effect of layout dependent Si distortion in wide isolation space. The mechanism of Si profile distortion in the wide isolation space by PR mask Si trench etch is well explained in this paper. Nitride masked Si trench etch as another Si trench etch scheme, so called hard mask scheme, is evaluated and proved to be significantly effective to reduce the leakage and improve the yield dramatically. This paper proposes that layout dependency on process performance and yield should be considered and stringently controlled when process scheme is decided.
2007-01-15