Shallow Trench Isolation Top Corner Rounding Using Si Soft Etching Following Diluted Hydrofluorine Solution
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2004-11-15
著者
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Ryu Hyuk
System Ic R&d Center Hynix Electronics Industries Co. Ltd.
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Jeong Yang
Department Of Electrical And Semiconductor Engineering Chonnam National University
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Jeong Y
Boe-hydis Co. Ltd. Kyungki‐do Kor
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Kwak J
Hanyang Univ. Seoul Kor
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MUN Seong
Process Engineering Dept. 5, MagnaChip Semiconductor Ltd.
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SHIN Kyeong
Process Engineering Dept. 5, MagnaChip Semiconductor Ltd.
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Mun Seong
Process Engineering Dept. 5 Magnachip Semiconductor Ltd.
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KWAK Jong
Process Engineering Dept. 5, MagnaChip Semiconductor., Ltd.
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YOON Ki
Process Engineering Dept. 5, HYNIX Electronics Industries Co., Ltd.
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Shin Kyeong
Process Engineering Dept. 5 Magnachip Semiconductor Ltd.
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Mun Seong
Process Engineering Dept. 5 Hynix Electronics Industries Co. Ltd.
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Kwak Jong
Process Engineering Dept. 5 Hynix Electronics Industries Co. Ltd.
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Jeong Yang
Department Of Electrical & Semiconductor Engineering Yosu National University
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Shin Kyeong
Process Engineering Dept. 5 Hynix Electronics Industries Co. Ltd.
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Yoon Ki
Process Engineering Dept. 5 Hynix Electronics Industries Co. Ltd.
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- Etch Defect Reduction Using SF_6/O_2 Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process
- Shallow Trench Isolation Top Corner Rounding Using Si Soft Etching Following Diluted Hydrofluorine Solution
- ZETA Potential Induced Particle Generation in SC2 Cleaning
- Pd-Ge-Au Based Hybrid Ohmic Contacts to High-Low Doped GaAs Field-Effect Transistor
- Etch Defect Reduction Using SF6/O2 Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process
- Layout Dependent Induced Leakage and its Prevention with Different Shallow Trench Isolation Schemes in 0.18 μm Dual Gate Complementary Metal Oxide Semiconductor Technology