Etch Defect Reduction Using SF_6/O_2 Plasma Cleaning and Optimizing Etching Recipe in Photo Resist Masked Gate Poly Silicon Etch Process
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2005-07-15
著者
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Jeong Yang
Department Of Electrical And Semiconductor Engineering Chonnam National University
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Jeong Y
Boe-hydis Co. Ltd. Kyungki‐do Kor
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Jeong Jae
Department Of Nuclear Medicine Seoul National University College Of Medicine
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Kwak J
Hanyang Univ. Seoul Kor
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MUN Seong
Process Engineering Dept. 5, MagnaChip Semiconductor Ltd.
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SHIN Kyeong
Process Engineering Dept. 5, MagnaChip Semiconductor Ltd.
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Mun Seong
Process Engineering Dept. 5 Magnachip Semiconductor Ltd.
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LEE Sung
Process Engineering Dept. 5, MagnaChip Semiconductor., Ltd.
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KWAK Jong
Process Engineering Dept. 5, MagnaChip Semiconductor., Ltd.
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