データの冗長性に着目したキャッシュの回路面積削減

概要

論文の詳細を見る
There's one reason to utilize cache that mitigates processor performance limitation comes from data transfer bandwidth. Recently, cache size expansion is required in this use because data transfer bandwidth requirement is increasing for recent large data size and multi-core trends. However, cache size expansion is unwelcome because it causes problems come from circuit area and power consumption viewpoint. This paper focuses a data redundancy with the goal of reducing cache size and proposes a mechanism that does not store redundant data into cache. The proposed mechanism divides data into Higher Bit and Lower Bit, that stored into Higher Cache and Lower Cache, respectively. We reduced Higher Cache size to half size by keeping 46% redundant data in Higher Bit area not to store into Higher Cache. The evaluation results show that the proposed mechanism increases IPC by 3.3% on average compared with same circuit area conventional cache under SPECCPU2000 benchmarks.