A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits
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概要
- 論文の詳細を見る
We investigate a design strategy for subthreshold circuits focusing on energy-consumption minimization and yield maximization under process variations. The design strategy is based on the following findings related to the operation of low-power CMOS circuits: (1) The minimum operation voltage (VDDmin) of a circuit is dominated by flip-flops (FFs), and VDDmin of an FF can be improved by upsizing a few key transistors, (2) VDDmin of an FF is stochastically modeled by a log-normal distribution, (3) VDDmin of a large circuit can be efficiently estimated by using the above model, which eliminates extensive Monte Carlo simulations, and (4) improving VDDmin may substantially contribute to decreasing energy consumption. The effectiveness of the proposed design strategy has been verified through circuit simulations on various circuits, which clearly show the design tradeoff between voltage scaling and transistor sizing.
- The Institute of Electronics, Information and Communication Engineersの論文
著者
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Ochi Hiroyuki
Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit
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Tsutsui Hiroshi
Department Of 1st Internal Medicine Cardiology Shinshu University School Of Medicine
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Sato Takashi
Department Of Applied Biochemistry And Food Science Saga University
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OCHI Hiroyuki
Department of Communications and Computer Engineering, the Graduate School of Informatics, Kyoto University
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KAWASHIMA Junya
Department of Communications and Computer Engineering, the Graduate School of Informatics, Kyoto University
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