Datapath-Layout-Driven Design for Low-Power FPGA Implementation (特集:電子システムの設計技術と設計自動化)

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The datapath is one of the main power-consuming parts in today's VLSIs. This paper proposes a new top-down field-programmable gate array (FPGA) design flow called Datapath-Layout-Driven Design (DLDD), which achieves low power by reducing the datapath wire length. While module partitioning and floor planning in the conventional design flow are based on the functional hierarchy, those in the DLDD flow are based on the "bit-slice" manner. After the module partitioning, the floor plan is designed and the optimal aspect ratio of the submodule is determined, followed by logic and layout synthesis. As an effect of DLDD flow, we can expect (1) lout power, because most data nets are short intra-module wires rather than long inter-module data buses, and (2) efficient layout, because all submodules are the same in size and shape. As a case study, DLDD was applied to the design of a 16-bit RISC processor, ASAP-1.1, for implementation on an FPGA device, Xilinx XC5210-6 PG223. We implemented and compared seven designs based on DLDD flow with different aspect ratios of submodules, along with one conventional design. In the best case in the experiments, the power consumption was successfully reduced by 25%.
1999-04-15