Hardware accelerator for robust object tracking using a cascade particle filter
スポンサーリンク
概要
著者
-
Ochi Hiroyuki
Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Universit
-
Miyamoto Ryusuke
Graduate School Of Information Sci. Nara Inst. Of Sci. And Technol.
関連論文
- Datapath-Layout-Driven Design for Low-Power FPGA Implementation (特集:電子システムの設計技術と設計自動化)
- Limited Sampling Strategy for Mycophenolic Acid in Japanese Heart Transplant Recipients : Comparison of Cyclosporin and Tacrolimus Treatment
- Relationship Between Acute Rejection and Cyclosporine or Mycophenolic Acid Levels in Japanese Heart Transplantation
- Pharmacokinetic Study and Limited Sampling Strategy of Cyclosporine in Japanese Heart Transplant Recipients
- A matched filter based round-trip delay measurement method for bi-directional satellite communication system with superposed transmission(Transmission Technology)
- Hardware Accelerator for Run-Time Learning Adopted in Object Recognition with Cascade Particle Filter
- Efficient Memory Organization Framework for JPEG2000 Entropy Codec
- Human papillomavirus infections among Japanese women : age-related prevalence and type-specific risk for cervical cancer
- Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device
- A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture(Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
- Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback(VLSI Architecture,VLSI Design and CAD Algorithms)
- An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- Hardware accelerator for robust object tracking using a cascade particle filter
- Stochastic Pedestrian Tracking Based on 6-Stick Skeleton Model(Image,Multimedia and Mobile Signal Processing)
- C-12-45 A sensor-based self-adjustment approach for controlling I/O buffer impedance
- Experimental Test of Frequency Reuse Interference Canceller in the Path Containing Nonlinear TWTA
- Nonlinear Compensations for Interference Canceller of Super-Positioning Satellite System
- Parallel Implementation Strategy for CoHOG-Based Pedestrian Detection Using a Multi-Core Processor
- Optimized Implementation of Pedestrian Tracking Using Multiple Cues on GPU
- Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element
- A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits
- Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method