InP HEMT Technology for High-Speed Logic and Communications(Session 2 Compound Semiconductor Devices I,AWAD2006)
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概要
- 論文の詳細を見る
As a review of the InP HEMT technology and its applications to logic ICs, the two-step-recess gate structure, which is now widely used in high-performance InP HEMTs, and its application to optoelectronic ICs are described. This paper also covers the topic of the gate delay analysis that reveals that the parasitic delay becomes the primary cause of the gate delay in sub-100-nm gate regime. For future challenge for logic applications, ways to reduce the off-state transistor current is also discussed.
- 社団法人電子情報通信学会の論文
- 2006-06-26
著者
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TOKUMITSU Masami
NTT Photonics Laboratories, NTT Corporation
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Suemitsu Tetsuya
Ntt Photonics Laboratories
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Suemitsu Tetsuya
Ntt Photonics Laboratories Ntt Corporation
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Tokumitsu Masami
Ntt Photonics Laboratories
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Tokumitsu Masami
Ntt Photonics Laboratories Ntt Corporation
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