VHDLの記述による、パイプライン回路の自動合成

概要

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In the design automation of ASIC with the behavioral specifications written in programming languages like VHDL, itis possible to create a pipelined circuit for pipeline iteration statements. Some thesis present scheduling technologies of pipeline circuits synthesis. But they do notexplain the way to extract and Create the pipeline from behavioral specifications. Some pipehne technologies have been well developed for general purpose compiler. However, most of them are based on so-called static data flow model. In this paper, we present a methodology,which is able to synthesis a pipeline processing circuit from its behavioral specification written in VHDL, which iteration range is not computable during compile-time.Mainly the following statements to appear in the VHDL language are discussed in this paper:・while iteration;・exit, which breaks an iteration;・if then-else and ・next.Section 2discusses the creation of pipeline from an iteration statement. Section 3presents a way to process theexit statement. Section 4and 5areabout the discussions of if-then-else and next statements, and in section 6,our future research projects are introduced.
一般社団法人情報処理学会の論文
1993-03-01