Verification and Violation Correction of Timing Constraints for Gate-Level Asynchronous Circuits (特集:システムLSIの設計技術と設計自動化)

概要

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Traditional asynchronous design methodologies basically create correct-by-design circuits with almost no assumptions on delay values in the circuit. However, this over-pessimism usually creates slow circuits. Recently, asynchronous design methodologies which utilize delay information and apply timing optimizations have been suggested. These timing optimizations bring new timing constraints to be observed especially after the layout phase. The aim of this work is to develop a timing verification methodology and an appropriate CAD framework for gate-level asynchronous circuits using welt-known static timing analysis method, which will be a bridge between asynchronous logic synthesis tools and common layout tools. Verification of timing constraints and correction of violations (if exist any) after layout are two main objectives. First, basic concepts for verification methodology will be given. Then, an algorithm for verification and violation correction of timing constraints for general asynchronous circuits is proposed. Later, asynchronous data-path circuits are examined in more detail. Finally, current status of the developed CAD framework is explained along some experimental results.
一般社団法人情報処理学会の論文
2003-05-15