Nanya T | Research Center For Advanced Science And Technology The University Of Tokyo

スポンサーリンク

概要

関連著者

もっと見る

著作論文

Design Method of High Performance and Low Power Functional Units Considering Delay Variations(Circuit Synthesis,VLSI Design and CAD Algorithms)
A Cascade ALU Architecture for Asynchronous Super-Scalar Processors (Special Issue on Low-Power High-Performance VLSI Processors and Technologies
Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design(IP Design)(VLSI Design and CAD Algorithms)
Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design
Verification and Violation Correction of Timing Constraints for Gate-Level Asynchronous Circuits (特集:システムLSIの設計技術と設計自動化)
Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
Verification of Timing Constraints for Fine-Grain Pielined Asynchronous Data-Path Circuits (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
3E-3 Layout Methodology for SDI Model Asynchronous Circuits
Evaluation of Checkpointing Mechanism on Score Cluster System(Dependable Software)(Dependable Computing)
Logic Optimization of Asynchronous Speed-Independent Circuits Using Transduction Methods (特集:システムLSIの設計技術と設計自動化)

もっと見る

スポンサーリンク