Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
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概要
- 論文の詳細を見る
Fine-grain pipelining is a method for concealing the overhead of idle phase in dual-rail encoded, 4-phase protocol asynchronous circuits. However, new timing constraints also emerge due to this optimization. In this manuscript, these constraints are examined for verifiability in local and global levels. A tool for automatic verification of these constraints is implemented and layout results for various data-path circuits are given.
- 社団法人電子情報通信学会の論文
- 2000-11-23
著者
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OZCAN Metehan
東京大学先端科学技術研究センター
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OZCAN Metehan
東京大学 先端科学技術研究センター
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NANYA Takashi
Research Center for Advanced Science and Technology, the University of Tokyo
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Oezcan M
Faculty Of Engineering The University Of Tokyo
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Ozcan Metehan
Research Center For Advanced Science And Technology The University Of Tokyo
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Nanya T
Research Center For Advanced Science And Technology The University Of Tokyo
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Nanya Takashi
Research Center For Advanced Science & Technology University Of Tokyo
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MOTOYAMA Katsuki
Research Center for Advanced Science and Technology, The University of Tokyo
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Motoyama Katsuki
Research Center For Advanced Science And Technology The University Of Tokyo
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