Device Performance and Reliability Considerations of Biaxially Strained Si by Wafer-Bonding-Technology

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概要

• 論文の詳細を見る
• 2007-09-19

著者

• Loh W.

  Institute Of Microelectronics

• YANG Rong

  Institute of Microelectronics

• LO G.

  Institute of Microelectronics

• KWONG D.-L.

  Institute of Microelectronics

• YANG R.

  Institute of Microelectronics

• CHAN D.

  National University of Singapore

• CHOO D.

  Institute of Microelectronics

• KOH S.

  Institute of Microelectronics

• ZHANG X.

  Institute of Microelectronics

• CAI C.

  Institute of High Performance Computing

• KWONG D-L

  Institute of Microelectronics

• Zhang X.

  Institute Of Dermatology Department Of Dermatology At First Hospital Anhui Medical University

関連論文

• Dopant Segregated Pt-Germanide Schottky S/D p-MOSFET with HfO_2/TaN gate on Strained Si-SiGe channel
• Bendable High-Performance Electronic Devices (Active Transistor, High-Density Interconnect and Passive-MIM Capacitors) on Flexible Organic-Substrate
• Ultra-Narrow Silicon Nanowire (-3nm) Gate-All-Around MOSFETs
• Overcoming Challenges in Metal Gate Etching for Sub-45nm Technology Node
• Creation of Strained and Relaxed SiGe films simultaneously through Ge condensation on SOI
• Fully-depleted ultra narrow (-10nm) body Gate-All-Around CMOS transistors
• Strained Ge-rich SiGe Nanowire pFETs with High-κ/Metal Gate Fabricated using Germanium Condensation Technique
• Si Quantum Dot TFT Nonvolatile Memory for System-On-Panel Applications
• Impacts of Body Contact Structures on SOI NMOSFET DC, RF, and 1/f Noise Characteristics
• Transport and Back-Gated Field Effect Characteristics of Si Nanowires Formed by Stress-Limited Oxidation
• Growth and Characterization of Germanium on Insulator (GOI) from Sputtered Ge by Novel Single and Dual Necking techniques
• A Novel Approach to fabricate High Ge content SiGe on Insulator from Amorphous SiGe deposited on SOI wafers
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• Visible Light Emission from Controlled α-Si/SiN Multi-layer Structures
• Practical Solutions to Enhance EWF Tunability of Ni FUSI Gates on HfO_2
• Highly Manufacturable CMOSFETs with Single High-k (HfLaO) and Dual Metal Gate Integration Process
• CMOS Compatible Si-Nanowire Inverter Logic Gate for Low Power Applications
• Device Performance and Reliability Considerations of Biaxially Strained Si by Wafer-Bonding-Technology
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