Low Latency Four-Flop Synchronizer with the Handshake Interface(Communications and Wireless Systems, <Special Section>Recent Advances in Circuits and Systems-Part 1)

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概要

• 論文の詳細を見る

• This letter presents a synchronizer and its handshake interface for bridging clock domains in SoC. The proposed scheme uses a double two-flop synchronizer operated at different clock edges respectively, based on a two-phase handshake protocol. Performance analysis shows that the proposed design reduces latency up to a clock cycle, while retaining its safety to a tolerable level.

• 社団法人電子情報通信学会の論文
• 2005-07-01

著者

• Lee Jeong

  Department of Obstetrics and Gynaecology, College od Medicine, Soonchunhyang University

• Kim Suk

  Department Of Obstetrics & Gynecology Graduate School Of Medicine Gachon University Of Medicine

• Kim Suk

  Department Of Information And Communications Gwangju Institute Of Science And Technology

• KIM Kiseon

  Department of Information and Communications, Gwangju Institute of Science and Technology

• Kim Suk

  Department Of Electronics Engineering Pusan National University

• Kim Kiseon

  Department Of Information And Communications Gwangju Institute Of Science And Technology

• Kim Kiseon

  Department Of Information And Communication At The Gwangju Institute Of Science And Technology (gist

• Lee Jeong

  Department Of Clothing And Textiles Gyeongsang National University

• Lee Jeong‐gun

  Hallym Univ. Kor

• Kim Suk

  Department Of Electronics Engineering And The Research Institute Of Computer Information And Communi

• Lee Jeong

  Department Of Animal Science And Biotechnology Kyungpook National University

• Lee Jeong

  Department Of Anesthesiology And Pain Medicine Yonsei University College Of Medicine

• Kim Suk

  Department of Ceramic Engineering, Yonsei University, 134 Shinchon-Dong, Seodaemun-Ku, Seoul 120-749, Korea

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