A Low Latency Asynchronous FIFO Combining a Wave Pipeline with a Handshake Scheme(VLSI Design Technology and CAD)

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概要

• 論文の詳細を見る

• This paper presents a new asynchronous FIFO design to reduce forward latency in a linear structure. The operation mode for each cell can be reconfigured dynamically as either of the two schemes, wave pipelining or handshaking, according to the data flow in the FIFO. The adoption of wave pipelining to the conventional self-timed FIFO can reduce the overhead of the handshaking as well as latching control in each stage. Initial pre-layout simulations indicate about two times of improvement on latency performance over a state-of-art asynchronous FIFO, while retaining its throughput.

• 社団法人電子情報通信学会の論文
• 2005-04-01

著者

• Lee Jeong

  Department of Obstetrics and Gynaecology, College od Medicine, Soonchunhyang University

• Kim Suk

  Department Of Obstetrics & Gynecology Graduate School Of Medicine Gachon University Of Medicine

• Kim Suk

  Department Of Information And Communications Gwangju Institute Of Science And Technology

• KIM Kiseon

  Department of Information and Communications, Gwangju Institute of Science and Technology

• Kim Suk

  Department Of Electronics Engineering Pusan National University

• Kim Kiseon

  Department Of Information And Communications Gwangju Institute Of Science And Technology

• Kim Kiseon

  Department Of Information And Communication At The Gwangju Institute Of Science And Technology (gist

• Lee Jeong

  Department Of Clothing And Textiles Gyeongsang National University

• Lee Jeong‐gun

  Hallym Univ. Kor

• Kim Suk

  Department Of Electronics Engineering And The Research Institute Of Computer Information And Communi

• Lee Jeong

  Department Of Animal Science And Biotechnology Kyungpook National University

• Lee Jeong

  Department Of Anesthesiology And Pain Medicine Yonsei University College Of Medicine

• Kim Suk

  Department of Ceramic Engineering, Yonsei University, 134 Shinchon-Dong, Seodaemun-Ku, Seoul 120-749, Korea

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