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Semiconductor Technology Academic Research Center (starc) | 論文
- An Experimental Study of Impact Ionization Phenomena in Sub-0.1μm Si MOSFETs
- A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills(VLSI Design Technology and CAD)
- Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG
- Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG
- Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm(Power/Ground Network, VLSI Design and CAD Algorithms)
- 100 nm-MOSFET Model for Circuit Simulation : Challenges and Solutions
- C-12-58 0.18-V Input Charge Pump with Forward Body Biasing
- Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90nm Technology and Beyond (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
- SAR ADC Architecture with Digital Error Correction
- A New Design Scheme for Logic Circuits with Single Electron Transistors
- A 1-V input, 0.2-V to 0.47-V output switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) for 57% ripple reduction (集積回路)
- Monte Carlo Simulation of Sub-0.1μm Devices with Schottky Contact Model (Special lssue on SISPAD'99)
- Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond (Soft Error, VLSI Design Technology in the Sub-100nm Era)
- Comprehensive Understanding of Electron and Hole Mobility Limited by Surface Roughness Scattering in Pure Oxides and Oxynitrides Based on Correlation Function of Surface Roughness
- Comprehensive Understanding of Electron and Hole Mobility Limited by Surface Roughness Scattering in Pure Oxides and Oxynitrides Based on Correlation Function of Surface Roughness
- Defects in Electroplated Cu and their Impact on Stress Migration Reliability
- 0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications
- 0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS
- A Statistical Quality Model for Delay Testing (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
- A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage