スポンサーリンク
Semiconductor Technology Academic Research Center (starc) | 論文
- High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM (Special Section on High Speed and High Density Multi Functional LSI Memories)
- A Second-Order Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm(Analog Circuits and Related SoC Integration Technologies)
- Complex Bandpass ΔΣAD Modulator Architecture without I, Q-Path Crossing Layout(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Quantum-Size Effect from Photoluminescence of Low-Temperature-Oxidized Porous Si
- A Novel False Lock Detection Technique for a Wide Frequency Range Delay-Locked Loop( Analog Circuit Techniques and Related Topics)
- SCR : SPICE Netlist Reduction Tool (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
- Post-BIST Fault Diagnosis for Multiple Faults
- High-Efficiency ZnCdSe/ZnSSe/ZnMgSSe Green Light-Emitting Diodes
- Synchrotron-Radiation-Induced Modification of Silicon Dioxide Film at Room Temperature : Beam Induced Physics and Chemistry
- Synchrotron-Radiation-Induced Modification of Silicon Dioxide Film at Room Temperature
- Synchrotron Radiation-Assisted Removal of Oxygen and Carbon Contaminants from a Silicon Surface
- 100 nm-MOSFET Model for Circuit Simulation : Challenges and Solutions(Devices and Circuits for Next Generation Multi-Media Communication Systems)
- Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an LSI Chip(Microelectronic Test Structures)
- Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances
- Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects
- High-Speed Continuous-Time Subsampling Bandpass ΔΣAD Modulator Architecture Employing Radio Frequency DAC(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses(Memory,Low-Power, High-Speed LSIs and Related Technologies)
- A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (V_) Variation(Novel Device Architectures and System Integration Technologies)
- Experimental Study of Impact Ionization Phenomena in Sub-0.1 μm Si Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs)