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Semiconductor Device Engineering Laboratory, Toshiba Corporation | 論文
- A Novel Sensing Scheme with On-Chip Page Copy for Flexible Voltage NAND Flash Memories (Special Issue on ULSI Memory Technology)
- Time Dependent Resistance Increase in Poly-Si Load Resistor due to Hydrogen Diffusion from Plasma-Enhanced Chemical Vapor Deposition Silicon Nitride Film in High Density Static Random Access Memories
- The Damage Energy Transfer to Interfacial Oxide by Phosphorus Ion Implantation for Small Geometry Polysilicon to Polysilicon Contact
- Evaluation of Spatial Distribution of Hole Traps Using Depleted Gate MOSFETs
- Interface State Generation Mechanism in MOSFET's during Substrate Hot-Electron Injection : Special Section : Solid State Devices and Materials 2 : Silicon Devices and Process Technologies
- A Novel Threshold Voltage Distribution Measuring Technique for Flash EEPROM Devices (Special Issue on Microelectronic Test Structure)
- Simultaneous Stress-Induced Al Extrusion and Void Formation Caused by High Temperature Annealing after Via-Hole Opening in Al Interconnects with Via-Holes
- Special and Embedded Memory Macrocells for Low-Cost and Low-Power in MPEG Environment (Special Issue on ULSI Memory Technology)
- Low-Voltage and Power CMOS Technology
- A 16-Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement (Special Issue on LSI Memories)
- Analysis of Narrow Emitter Effects in Half-Micron Bipolar Transistors
- The Effects of Al(111) Crystal Orientation on Electromigration in Half-Micron Layered Al Interconnects
- Process and Device Technologies of CMOS Devices for Low-Voltage Operation (Special Section on Low-Power and Low-Voltage Integrated Circuits)
- Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90nm Technology and Beyond (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
- 0.1 μm Fine-Pattern Fabrication Using Variable-Shaped Electron Beam Lithography
- Novel Silicon-Containing Negative Resist for Bilayer Application in Electron Beam Direct Writing