Process and Device Technologies of CMOS Devices for Low-Voltage Operation (Special Section on Low-Power and Low-Voltage Integrated Circuits)

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概要

• 論文の詳細を見る

• Process and device technologies of CMOS devices for low-voltage operation are described. First, optimum power-supply voltage for CMOS devices is examined in detail from the viewpoints of circuit performance, device reliability and power dissipation. As a result, it is confirmed that power-supply voltage can be reduced without any speed loss of the CMOS device. Based upon theoretical understanding, the author suggests that lowering threshold voltage and reduction of junction capacitance are indispensable for CMOS devices with low-voltage supply, in order to improve the circuit performance, as expected from MOS device scaling. Process and device technologies such as Silicon On Insulator (SOI) device, low-temperature operation and CMOS Shallow Junction Well FET (CMOS-SJET) structure are reviewed for reduction of the threshold voltage and junction capacitance which lead to high-speed operation of the CMOS device at low-voltage.

• 社団法人電子情報通信学会の論文
• 1993-05-25

著者

• KAKUMU Masakazu

  Semiconductor Device Engineering Laboratory, Toshiba Corporation

• Kakumu M

  Toshiba Corp. Kawasaki‐shi Jpn

• Kakumu Masakazu

  Semiconductor Device Engineering Laboratory Toshiba Corporation

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• Low-Voltage and Power CMOS Technology
• Process and Device Technologies of CMOS Devices for Low-Voltage Operation (Special Section on Low-Power and Low-Voltage Integrated Circuits)

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