Design Methodology of Deep Submicron CMOS Devices for 1 V Operation (Special Issue on Low-Power LSI Technologies)

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概要

• 論文の詳細を見る

• A design methodology of high performance deep submicron CMOS in very low voltage operation has been proposed from low power dissipation point of view. In low voltage operation, threshold voltage is restricted by performance,stability of CMOS circuits and power dissipation caused by standby and switching transient current. As a result, threshold voltage is established to be O.15 V even at l V operation from these requirements. Moreover, according to this design, 0.15μm CMOS was fabricated with reduction of parasitic effects. It achieved propagation delay time 50 psec at l V operation. This results confirms that this design methodology is promising to achieve high performance deep submicron CMOS devices for low power dissipation.

• 1996-12-25

著者

• Kakumu M

  Toshiba Corp. Kawasaki‐shi Jpn

• Kakumu Masakazu

  Lsi Division Ii Toshiba Corporation

• Oyamatsu Hisato

  Ulsi Device Engineering Laboratory Toshiba Corporation

• Oyamatsu H

  Faculty Of Science Osaka University

• KINUGAWA Masaaki

  ULSI Device Engineering Laboratory, Toshiba Corporation

• Kinugawa Masaaki

  Ulsi Device Engineering Laboratory Toshiba Corporation

関連論文

• Design Methodology of Deep Submicron CMOS Devices for 1 V Operation (Special Issue on Low-Power LSI Technologies)
• Low-Voltage and Power CMOS Technology
• X-Ray Diffraction Study on Symmethry of β-Mn Structure
• High-Density Full-CMOS SRAM Cell Technology with a Deep Sub-Micron Spacing between nMOS and pMOSFET (Special Section on High Speed and High Density Multi Functional LSI Memories)
• Process and Device Technologies of CMOS Devices for Low-Voltage Operation (Special Section on Low-Power and Low-Voltage Integrated Circuits)

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