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Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation | 論文
- Sub-1.3 nm Amorphous Tantalum Pentoxide Gate Dielectrics for Damascene Metal Gate Transistors
- Sub 1.3nm Amorphous Ta_2O_5 Gate Dielectrics for Damascene Metal Gate Transistor
- Highly Uniform Low-Pressure Chemical Vapor Deposition (LP-CVD) of Si_3N_4 Film on Tungsten for Advanced Low-Resistivity "Polymetal" Gate Interconnects
- Plasma-Damage-Free Gate Process Using Chemical Mechanical Polishing for 0.1 μm MOSFETs
- Plasma Damage Free Gate Process Using CMP for 0.1um MOSFETs
- Influence of Lattice Distortion and Oxygen Defects in BST Films for Memory Capacitors
- (Ba, Sr)TiO_3 Stacked Capacitor Technology for 0.13μm-DRAMs and Beyond
- Effects of Cleavage on Local Cross-Sectional Stress Distribution in Trench Isolation Structure
- Effects of Cleavage on Local Cross-Sectional Stress Distribution in Trench Isolation Structure
- Improved Ti Self-Aligned Silicide Technology Using High Dose Ge Pre-Amorphization for 0.10 μm CMOS and Beyond
- New PentaCoordinated Si(PCS) Model for SiN CVD Mechanism
- Mechanism of Defect Formation during Low-Temperature Si Epitaxy on Clean Si Substrate
- Dominant Factor for the Concentration of Phosphorus Introduced by Vapor Phase Doping (VPD)
- Dominant Factor for the Concentration of Phosphorus Introduced by Vapor Phase Doping
- Ferroelectric Properties of Pb(Zi, Ti)O_3 Capacitor with Thin SrRuO_3 Films within Both Electrodes
- Reliable High-k TiO_2 Gate Insulator Formed by Ultrathin TiN Deposition and Low Temperature Oxidation
- Miniaturized Stepped Impedance Resonators with a Double Coaxial Structure and Their Application to Bandpass Filters
- Highly Uniform Deposition of LP-CVD 3i3N4 Films on Tungsten for Advanced Low Resistivity "Poly-Metal" Gate Interconnects
- Correlation of W-Si-N Film Microstructure with Barrier Performance against Cu Diffusion
- Correlation of W-Si-N Film Microstructure with Barrier Performance against Cu Diffusion