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Device Development Center Hitachi Ltd. | 論文
- The Analysis of the Defective Cells Induces by COP in a 0.3-micron-technology Node DRAM
- The Analysis of Defective Cell Induced by COP in 0.3 microns Technology Node DRAM
- Fast Computation of Microscale Temperature Distribution in LSI Chips
- DMA SRAM TEGにより解析したSRAMのスタティックノイズマージンにおけるDIBLばらつきの影響(IEDM特集(先端CMOSデバイス・プロセス技術))
- DFT Timing Design Methodology for Logic BIST(Timing Verification and Test Generation)(VLSI Design and CAD Algorithms)
- DFT Timing Design Methodology for Logic BIST
- Estimation of Subsurface Fracture Roughness by Polarimetric Borehole Radar(Special Issue on Problems of Random Scattering and Electromagnetic Wave Sensing)
- High-Accuracy Analysis of Interconnect Capacitance for Floating Metal Fills
- Quanititative Study of Implanted Gold Atoms in Silicon p^+-n Junctions by Measurement of the Thermally-Stimulated Current
- Uptake of Lysine by Wild-Type and S-(2-Aminoethyl)-L-cysteine-Resistant Suspension-Cultured Cells of Triticum aestivum
- +3 V/-3 V Operation 1.2 Gbps Write Driver for Hard Disk Drives(Low-Power System LSI, IP and Related Technologies)
- Warpage of Czochralski-Grown Silicon Wafers as Affected by Oxygen Precipitation
- A 156Mb/s Interface CMOS LSI for ATM Switching Systems
- Sub-Quarter-Micron Pt Etching Technology Using Electron Beam Resist with Round-Head
- 微細MOSトランジスタにおけるDIBLおよび電流立上り電圧ばらつきの統計解析(低電圧/低消費電力技術,新デバイス・回路とその応用)
- Takeuchiプロットを用いたHigh-k/Metal-Gate MOSFETのばらつき評価(低電圧/低消費電力技術,新デバイス・回路とその応用)
- 微細MOSトランジスタにおけるDIBLおよび電流立上り電圧ばらつきの統計解析(低電圧/低消費電力技術,新デバイス・回路とその応用)
- Takeuchiプロットを用いたHigh-k/Metal-Gate MOSFETのばらつき評価(低電圧/低消費電力技術,新デバイス・回路とその応用)
- 完全空乏型SOI MOSFETにおける特性ばらつきとランダムテレグラフノイズ(プロセス科学と新プロセス技術)
- Copper Metallization for High-Speed ECL-CMOS LSI's