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Central Research Laboratory, HITACHI, Ltd. | 論文
- Electric-Energy Generation through Variable- Capacitive Resonator for Power-Free LSI(Low-Power System LSI, IP and Related Technologies)
- Long-Retention-Time, High-Speed DRAM Array with 12-F^2 Twin Cell for Sub 1-V Operation(Memory,Low-Power, High-Speed LSIs and Related Technologies)
- Low ACPR Characteristics for WCDMA Applications of SiGe:C HBT Devices with Small Emitter Capacitance(Advanced RF Technologies for Compact Wireless Equipment and Mobile Phones)
- Dynamic Terminations for Low-Power High-Speed Chip Interconnection in Portable Equipment
- Buried J-FET Powered Static RAM Cell : A-5: MEMORY DEVICES
- High Packing Density, high Speed CMOS (Hi-CMOS) Device technology : A-3: MOS DEVICE AND LIST (3)
- Development and Fabrication of Digital Neural Network WSIs (Special Issue on New Architecture LSIs)
- Photocurrent and Photoluminescence in InGaAs/GaAs Multiple Quantum Well Solar Cells
- Vertical Transport Properties of Photogenerated Carrier in InGaAs/GaAs Strained Multiple Quantum Welts
- Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
- Crystal Structure Change of GaAs and InAs Whiskers from Zinc-Blende to Wurtzite Type
- Behavior of Active and Inactive Boron in Si Produced by Vapor-Phase Doping during Subsequent Hydrogen Annealing
- Subquarter-Micrometer PMOSFET's with 50-nm Source and Drain Formed by Rapid Vapor-Phase Doping (RVD) (Special Issue on Quarter Micron Si Device and Process Technologies)
- Real Time Magnetic Imaging by Spin-Polarized Low Energy Electron Microscopy with Highly Spin-Polarized and High Brightness Electron Gun
- The Umbrella Cell : A High-Density 2T Cell for SOC Applications(Memory, Low-Power LSI and Low-Power IP)
- FOREWORD (Special Issue on ULSI Memory Technology)
- Sub 1V Swing Internal Bus Architecture for Future Low-Power ULSI's (Special Section on the 1992 VLSI Circuits Symposium)
- A Robust Array Architecture for a Capacitorless MISS Tunnel-Diode Memory(Integrated Electronics)
- The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
- Electrostrictive Materials for Ultrasonic Probes in the Pb(Mg_Nb_)O_3-PbTiO_3 System : F: FERROELECTRIC MATERIALS