Characterization and Modeling of Pattern Ground Shield and Silicon-Substrate Effects on Radio-Frequency Monolithic Bifilar Transformers for Ultra-Wide Band Radio-Frequency Integrated Circuit Applications
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概要
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In this paper, an analysis of the effects of pattern-ground-shield (PGS) and silicon-substrate on the performances of RF monolithic bifilar transformers are demonstrated. It was found that high-quality-factor and low-power-loss transformers can be obtained if the optimized PGS (OPGS) of polysilicon is adopted and the complementary metal–oxide–semiconductor (CMOS)-process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the transformers completely. OPGS means that the redundant PGS of a traditional complete PGS (CPGS), which is right below the spiral metal lines of the transformer, is removed for the purpose of reducing the large parasitic capacitance. The results show that, if the OPGS was adopted and the backside ICP etching was done, a 253.6% (from 3.79 to 13.4) increase in Q-factor, a 14% (from 0.7 to 0.798) increase in magnetic-coupling factor ($k_{\text{Im}}$), a 51.1% (from 0.55 to 0.831) increase in maximum available power gain ($G_{\text{Amax}}$), and a 1.79 dB (from 2.597 to 0.807) reduction in minimum noise factor ($\mathrm{NF}_{\text{min}}$) were achieved at 8 GHz for a bifilar transformer with an overall dimension of $230\times 215$ μm2.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2007-01-15
著者
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Wang Tao
Graduate Institute Of Electronics Engineering And Department Of Electrical Engineering National Taiw
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Liang Hsiao-bin
Department Of Electrical Engineering National Chi Nan University
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LU Shey-Shi
Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Tai
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Chen Chi-chen
Department Of Electrical Engineering National Chi Nan University
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Lin Yo-sheng
Department Of Electrical Engineering National Chi-nan University
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Lu Shey-Shi
Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.
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Lin Yo-Sheng
Department of Electrical Engineering, National Chi Nan University, Puli, Taiwan, R.O.C.
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Chen Chi-Chen
Department of Electrical Engineering, National Chi Nan University, Puli, Taiwan, R.O.C.
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Liang Hsiao-Bin
Department of Electrical Engineering, National Chi Nan University, Puli, Taiwan, R.O.C.
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Wang Tao
Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.
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