Impact of Flash Lamp Annealing on 20-nm-Gate-Length Metal Oxide Silicon Field Effect Transistors
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概要
- 論文の詳細を見る
The advantages of using the new flash lamp annealing (FLA) technology and a shallow junction with the consequent low sheet resistivity for metal oxide silicon field effect transistors (MOSFETs) with gate length ($L$) of 20 nm were clarified by computer simulations based on MOSFETs fabricated with FLA for the first time. In contrast to spike annealing, the shallow junction realized by applying FLA to pMOSFET fabrication enabled the suppression of $|I_{\text{off}}|$ with a low channel surface dopant concentration, thus providing a higher mobility value and a higher drive current. FLA is promising for improving the performance of sub-30-nm-gate-length MOSFETs.
- Japan Society of Applied Physicsの論文
- 2003-10-01
著者
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NISHINOHARA Kazumi
Process and Manufacturing Engineering Center, Semiconductor Company, Toshiba Corp.
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Suguro Kyoichi
Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation
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Ito Takayuki
Process And Manufacturing Engineering Center Semiconductor Company Toshiba Corp.
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Suguro Kyoichi
Process and Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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Nishinohara Kazumi
Process and Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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Itani Takaharu
Process and Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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