An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA
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概要
- 論文の詳細を見る
Synchronous design methodology is widely used for todays digital circuits. However, it is difficult to reuse a highly-optimized synchronous module for a specific clock frequency to other systems with different global clocks, because logic depth between FFs should be tailored for the clock frequency. In this paper, we focus on asynchronous design, in which each module works at its best performance, and apply it to an IEEE-754-standard single-precision floating-point divider. Our divider is ready to be built into a system with arbitrary clock frequency and achieves its peak performance and area- and power-efficiency. This paper also reports an implementation result and performance evaluation of the proposed divider on a Xilinx Virtex-4 FPGA. The evaluation results show that our divider achieves smaller area and lower power consumption than the synchronous dividers with comparable throughput.
著者
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Ochi Hiroyuki
Graduate School Of Engineering Hiroshima University
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NAKAMURA Yukihiro
Research Organization of Science and Engineering, Ritsumeikan University
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Nakamura Yukihiro
Research Organization Of Science And Engineering Ritsumeikan University
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Nakamura Yukihiro
Graduate School Of Sciences And Technology Niigata University:institute For Human Science And Biomed
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Nakamura Yukihiro
The Department Of Communications And Computer Engineering Graduate School Of Informatics Kyoto Unive
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中村 行宏
京都高度技術研究所
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Hiromoto Masayuki
Graduate School of Informatics, Kyoto University
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