Simple Formulas for Interconnect Delay and Crosstalk Considering the Transition Time of Ramp Signals

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概要

• 論文の詳細を見る

• A analytical formula is proposed for the delay of the distributed RC interconnect line driven by an input waveform having a finite transition time for the first time. Formulas for crosstalk noise between two capacitive coupling lines are derived from the formula for the delay. The formulas for the delay and crosstalk noise are applied to several conditions under transition times, interconnect lengths and buffer sizes. The results are compared with SPICE simulations. Through this work, it is found that the derived closed-form formulas are well agreed with SPICE simulations so that they will be useful for the estimation of delays and crosstalks of long interconnect lines in VLSI circuits.

• 社団法人電子情報通信学会の論文
• 1999-07-23

著者

• Choi J‐s

  Hyundai Electronics Ind. Co. Ltd. Icheon Kor

• Lee S‐h

  Memory Research And Development Division Hyundai Electronics Industries

• Lee Seong-hoon

  Dram Design Memory Product & Technology Development Division Hyundai-electronics Industries

• Lee Sang-ho

  Pg.1 R&d Division Lg Semicon Co. Ltd.

• Wee Jae-Kyung

  DRAM Design, Memory Product & Technology Development Division, Hyundai-Electronics Industries

• Lee Chang-Hyuk

  DRAM Design, Memory Product & Technology Development Division, Hyundai-Electronics Industries

• Choi Joo-Sun

  DRAM Design, Memory Product & Technology Development Division, Hyundai-Electronics Industries

• Wee J‐k

  Hynix Semiconductor Icheon Kor

• Lee Chang-hyuk

  Dram Design Memory Product & Technology Development Division Hyundai-electronics Industries

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