Wee J‐k | Hynix Semiconductor Icheon Kor

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Simple Formulas for Interconnect Delay and Crosstalk Considering the Transition Time of Ramp Signals
Simple Formulas for Interconnect Delay and Crosstalk Considering the Transition Time of Ramp Signals
Simple Formulas for Interconnect Delay and Crosstalk Considering the Transition Time of Ramp Signals
Measurement-Based Line Parameter Extraction Method for Multiple-Coupled Lines in Printed Circuit Boards(Special Issue on Microwave and Millimeter Wave Technology)
Power Distribution Network Design Using Network Synthesis in High-Speed Digital Systems(Microwaves, Millimeter-Waves)
Pipelined Wake-Up Scheme to Reduce Power Line Noise for Block-Wise Shutdown of Low-Power VLSI Systems(Low-Power System LSI, IP and Related Technologies)
A Temperature- and Supply-Insensitive Fully On-Chip 1Gb/s CMOS Open-Drain Output Driver for High-Bandwidth DRAMs
Fully On-Chip Current Controlled Open-Drain Output Driver for High-Bandwidth DRAMs

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