Lee Seong-hoon | Dram Design Memory Product & Technology Development Division Hyundai-electronics Industries

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著作論文

Characteristics of Dual Polymetal(W/WNx/Poly-Si)Gate Complementary Metal Oxide Semiconductor for 0.1 μm Dynamic Random Access Memory Technology
Characteristics of Dual Polymetal (W/WNx/Poly-Si) Gate CMOS for 0.1μm DRAM Technology
A 0.1μm CMOS Technology using W/WN_x/Polysilicon Dual Gate Electrode for 4G DRAM and Beyond
A 0.1μm CMOS Technology using W/WN_x/Polysilicon Dual Gate Electrode for 4G DRAM and Beyond
A 0.1μm CMOS Technology using W/WN_x/Polysilicon Dual Gate Electrode for 4G DRAM and Beyond
Simple Formulas for Interconnect Delay and Crosstalk Considering the Transition Time of Ramp Signals
Simple Formulas for Interconnect Delay and Crosstalk Considering the Transition Time of Ramp Signals
Simple Formulas for Interconnect Delay and Crosstalk Considering the Transition Time of Ramp Signals
Moisture Induced Hump Characteristics of Shallow Trench-Isolated Sub-1/4μm nMOSFET
Moisture Induced Hump Characteristics of Shallow Trench-Isolated Sub-1/4μm nMOSFET
Moisture Induced Hump Characteristics of Shallow Trench-Isolated Sub-1/4 μm nMOSFET

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