Moisture Induced Hump Characteristics of Shallow Trench-Isolated Sub-1/4 μm nMOSFET

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In this paper, short-channel hump characteristics of nMOSFETs (W/L_<eff>=15/0.25um) fabricated with 0.23um STI DRAM technology, induced by moisture not by the field oxide recess, have been firstly investigated. LPCVD TEOS(LP-TEOS) ILD over poly-Si gate of nMOSFETs generates moisture, which isn't diffused out of LP-TEOS layer due to the upper capping SiN layer, generally used for etch stopper layer during formation of the DRAM cell capacitor, but diffuses into the gate edge, and induces short-channel humps. Based on the extensive experimental results, we obviously show that the short-channel hump phenomena are caused by diffusion of moisture from LP-TEOS. To eliminate moisture in the LP-TEOS layer by out-gassing, the vacuum anneal or RTP prior to the deposition of the capping SiN(300Å) layer was carried out. As the result, short-channel humps of nMOSFETs were successfully suppressed.
社団法人電子情報通信学会の論文
1999-07-23