A 0.1μm CMOS Technology using W/WN_x/Polysilicon Dual Gate Electrode for 4G DRAM and Beyond

概要

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A 0.1μm CMOS Technology using W/WN_x/Polysilicon dual gate electrode for 4G DRAM is presented in this paper. The polymetal(W/WN_x/Polysilicon) gate is defined down to 0.12μm and it shows 3.3Ω/□ sheet resistance. We make the surface channel pMOSFET(SC-pMOSFET) with 4.5nm pure oxide gate dielectric. It shows high short channel immunity, no boron penetration and good charge-to-breakdown(Q_<bd>) distribution.
社団法人電子情報通信学会の論文
1999-07-22