Characteristics of Dual Polymetal (W/WNx/Poly-Si) Gate CMOS for 0.1μm DRAM Technology
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概要
- 論文の詳細を見る
- 1999-09-20
著者
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Hahn Dae-hee
Memory Research And Development Division Hyundai Electronics Industries
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Kim Seon-soon
Memory Research And Development Division Hyundai Electronics Industries
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Kim Hyung-duck
Memory Research And Development Division Hyundai Electronics Industries
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Lee S‐h
Memory Research And Development Division Hyundai Electronics Industries
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Choi Jun-oh
Memory Research And Development Division Hyundai Electronics Industries
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Lee Seong-hoon
Dram Design Memory Product & Technology Development Division Hyundai-electronics Industries
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Lee Sang-ho
Pg.1 R&d Division Lg Semicon Co. Ltd.
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Chang Sung-keun
Memory Research And Development Division Hyundai Electronics Industries
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Kim Y‐h
Naju Coll. Chonnam Kor
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KIM Yong-Hae
Semiconductor Advanced Research Division, Hyundai Electronics Industries
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CHANG Sung-Keun
Semiconductor Advanced Research Division, Hyundai Electronics Industries
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KIM Seon-Soon
Semiconductor Advanced Research Division, Hyundai Electronics Industries
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CHOI Jun-Gi
Semiconductor Advanced Research Division, Hyundai Electronics Industries
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LEE Sang-Hee
Semiconductor Advanced Research Division, Hyundai Electronics Industries
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HAHN Dae-Hee
Semiconductor Advanced Research Division, Hyundai Electronics Industries
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KIM Hyung-Duck
Semiconductor Advanced Research Division, Hyundai Electronics Industries
関連論文
- Characteristics of Dual Polymetal(W/WNx/Poly-Si)Gate Complementary Metal Oxide Semiconductor for 0.1 μm Dynamic Random Access Memory Technology
- Characteristics of Dual Polymetal (W/WNx/Poly-Si) Gate CMOS for 0.1μm DRAM Technology
- A 0.1μm CMOS Technology using W/WN_x/Polysilicon Dual Gate Electrode for 4G DRAM and Beyond
- A 0.1μm CMOS Technology using W/WN_x/Polysilicon Dual Gate Electrode for 4G DRAM and Beyond
- A 0.1μm CMOS Technology using W/WN_x/Polysilicon Dual Gate Electrode for 4G DRAM and Beyond
- Simple Formulas for Interconnect Delay and Crosstalk Considering the Transition Time of Ramp Signals
- Simple Formulas for Interconnect Delay and Crosstalk Considering the Transition Time of Ramp Signals
- Simple Formulas for Interconnect Delay and Crosstalk Considering the Transition Time of Ramp Signals
- Moisture Induced Hump Characteristics of Shallow Trench-Isolated Sub-1/4μm nMOSFET
- Moisture Induced Hump Characteristics of Shallow Trench-Isolated Sub-1/4μm nMOSFET
- Moisture Induced Hump Characteristics of Shallow Trench-Isolated Sub-1/4 μm nMOSFET