Pipelined Wake-Up Scheme to Reduce Power Line Noise for Block-Wise Shutdown of Low-Power VLSI Systems(<Special Section>Low-Power System LSI, IP and Related Technologies)
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概要
- 論文の詳細を見る
Block-wise shutdown of idle functional blocks in VLSI systems is a promising approach to reduce power consumption. Especially, multi-threshold voltage CMOS (MTCMOS) is widely accepted to save leakage power during idle time. As operating frequency increases, it requires short wake-up time to use the shutdown block in time. However, short wake-up time of a large block causes large current surge during wake-up process. This often leads to system malfunction due to severe power line noise. This is one of the serious problems for practical implementation of MTCMOS block-wise shutdown. This letter proposes an effective wake-up scheme for block-wise shutdown of low-power VLSI systems. It exploits pipelined wake-up strategy that reduces current surge during wake-up process. In this letter, the proposed scheme was analyzed and simulated from the viewpoint of power distribution network. To verify its validity, it was applied to a multiplier block in Compact Flash controller chip on a test board. According to the simulation results of equivalent R, L, and C modeling, the proposed scheme achieved significant improvement over conventional concurrent shutdown schemes.
- 社団法人電子情報通信学会の論文
- 2004-04-01
著者
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Wee J‐k
Hynix Semiconductor Icheon Kor
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Kim Y‐j
Memory Research & Development Division Hynix Semiconductor Inc.
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KIM Yong-Ju
Memory Research & Development Division, Hynix Semiconductor Inc.
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LEE Seongsoo
School of Electronic Engineering, Soongsil University
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CHOI Jin-Hyeok
Center for Collaboration Research, University of Tokyo
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WEE Jae-Kyung
College of Information and Electronics Engineering, Hallym University
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Kim Yong-ju
Memory Research & Development Division Hynix Semiconductor Inc.
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Kim Yong-ju
Department Of Eecs Korea Advanced Institute Of Science And Technology
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Kim Yong-ju
Memory R&d Center Hynix
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Lee Seongsoo
School Of Electronic Engineering Soongsil University
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Choi Jin-hyeok
Center For Collaboration Research University Of Tokyo
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KIM Yong-Ju
Memory R&D Center
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