A VLSI Architecture for Motion Estimation Core Dedicated to H.263 Video Coding(Special Issue on Multimedia, Network, and DRAM LSIs)
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概要
- 論文の詳細を見る
A VLSI architecture of a motion estimator is described dedicatedly for the H.263 low bitrate video coding. Adopting an efficient hierarchical search algorithm, a new motion estimator yields high quality vectors with small area occupancy and at a low operation frequency. A one-dimensional PE (Processing Element) array is devised to be tuned to the H.263 encoding, which treats both the advanced prediction mode and the PB-frame mode. The proposed motion estimation core is integrated in 1.55mm^2 by using 0.35μm CMOS 3LM technology, which operates at 15MHz, and hence enables the realtime motion estimation of QCIF pictures.
- 社団法人電子情報通信学会の論文
- 1998-05-25
著者
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Onoye Takao
The Graduate School Of Informatics Dept.communications And Computer Engineering Kyoto University
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Shirakawa Isao
Graduate School Of Applied Informatics University Of Hyogo
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Fujita Gen
Osaka University
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Shirakawa I
Graduate School Of Applied Informatics University Of Hyogo
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FUJITA Gen
the Center for Advanced Research Projects, Osaka University
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SHIRAKAWA Isao
the Graduate School of Engineering, Osaka University
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Shirakawa Isao
The Graduate School Of Engineering Dept.information Systems Engineering Osaka University
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