Shirakawa I | Graduate School Of Applied Informatics University Of Hyogo

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概要

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著作論文

Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP@HL (Special Section on Digital Signal Processing)
A 25kV ESD Proof LDMOSFET with a Turn-on Discharge MOSFET
A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS
A 200V CMOS SOI IC with Field-Plate Trench Isolation for EL Displays
A Single Chip Automotive Control LSI Using SOI BiCDMOS
Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Real-Time Human Object Extraction Method for Mobile Systems Based on Color Space Segmentation(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Object Sharing Scheme for Heterogeneous Environment
Wireless Digital Video Transmission System Using IEEE802.11b PHY with Error Correction Block Based ARQ Protocol(Special Issue on Mobile Multimedia Communications)
Error Detection by Digital Watermarking for MPEG-4 Video Coding(Special Section on Papers Selected from ITC-CSCC 2001)
An Embedded Zerotree Wavelet Video Coding Algorithm with Reduced Memory Bandwidth
A VLSI Architecture for Motion Estimation Core Dedicated to H.263 Video Coding(Special Issue on Multimedia, Network, and DRAM LSIs)
Single Chip Implementation of MPEG2 Decoder for HDTV Level Pictures (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
High-Level Synthesis of a Multithreaded Processor for Image Generation
Area-Efficient Reconfigurable Architecture for Media Processing
Implementation of Java Accelerator for High-Performance Embedded Systems(Simulation Acceletor)(VLSI Design and CAD Algorithms)
Implementation of Java Accelerator for High-Performance Embedded Systems
A Novel Dynamically Reconfigurable Hardware-based Cipher (特集システムLSIの設計技術と設計自動化)

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