Code Efficiency Evaluation for Embedded Processors(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)

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概要

• 論文の詳細を見る

• This paper evaluates the code efficiency of the ARM, Java, and x86 instruction sets by compiling the SPEC CPU95/CPU2000/JVM98 and CaffeineMark benchmarks, from the aspects of code sizes, basic block sizes, instruction distributions, and average instruction lengths. As a result, mainly because (i) the Java architecture is a stack machine, (ii) there are only four local variables which can be accessed by a 1-byte instruction, and (iii) additional instructions are provided for the network security, the code efficiency of Java turns out to be inferior to that of ARM Thumb. Moreover, through this efficiency analysis it should be stressed that there exists the high potential of constructing a more efficient code architecture by taking minute account of the customization of an instruction set as well as the number of registers.

• 社団法人電子情報通信学会の論文
• 2002-04-01

著者

• TAKEUCHI Yoshinori

  Graduate School of Information Science and Technology, Osaka University

• Shirakawa Isao

  Graduate School Of Applied Informatics University Of Hyogo

• Shirakawa Isao

  Graduate School Of Engineering Osaka University

• MIKI Morgan

  Graduate School of Engineering, Osaka University

• Miyamoto Shingo

  Graduate School Of Engineering Osaka University

• SAKAMOTO Mamoru

  System LSI Development Center,Mitsubishi Electric Corporation

• YOSHIDA Toyohiko

  Mobile Communication Business Division, Mitsubishi Electric Corporation

• Takeuchi Yoshinori

  Graduate School Of Information Science And Technology Osaka University

• Miki Morgan

  Graduate School Of Engineering Osaka University

• Yoshida Toyohiko

  Mobile Communication Business Division Mitsubishi Electric Corporation

• Sakamoto Mamoru

  System Lsi Development Center Mitsubishi Electric Corporation

• Takeuchi Yoshinori

  Graduate School Of Engineering Science Osaka University

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