JPEG Encoder Design Space Exploration Using the ASIP Development System: PEAS-3 (特集:システムLSIの設計技術と設計自動化)
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概要
- 論文の詳細を見る
In this paper, JPEG encoder application, one of DSP applications, was designed using the ASIP development system: PEAS-III. Instructions for JPEG encoder, such as DCT instruction, and butterfly instructions, were added to the initial design. Area, performance, and power consumption of processors were estimated using generated HDL description, compiler, and assembler. From experimental results, 12 architectures can be designed in 16 hours, and designer can select an optimal architecture that matches design constraints considering hardware cost, clock frequency and execution cycles.
- 一般社団法人情報処理学会の論文
- 2003-05-15
著者
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TAKEUCHI Yoshinori
Graduate School of Information Science and Technology, Osaka University
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IMAI Masaharu
Graduate School of Information Science and Technology, Osaka University
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Imai M
Graduate School Of Information Science Technology Osaka University
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Imai Masaharu
Department Of Information And Computer Sciences Toyohashi University Of Technology
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Imai Masaharu
Graduate School Of Information Science And Technology Osaka University
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Takeuchi Yoshinori
Graduate School Of Information Science And Technology Osaka University
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Takeuchi Yoshinori
Graduate School Of Information Science Technology Osaka University
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Takeuchi Yoshinori
Advanced Technology Research Laboratories Matsushita Electric Industrial Co. Ltd.
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Kobayashi Shinsuke
Graduate School Of Engineering And Science Osaka University
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MITA KENTARO
Graduate School of Engineering and Science, Osaka University
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Mita Kentaro
Graduate School Of Engineering And Science Osaka University
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Takeuchi Yoshinori
Graduate School Of Engineering Science Osaka University
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Imai Masaharu
Graduate School of Electrical and Electronic Engineering Kogakuin University
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