An Instruction Set Optimization Algorithm for Pipelined ASIPs
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概要
- 論文の詳細を見る
This paper proposes a new method to design an optimal pipelined instruction set processor using a formal HW/SW codesign methodology. A HW/SW partitioning algorithm for selecting an optimal pipelined architecture is introduced. The codesign task addressed in this paper is to find a set of hardware implemented operations to achieve the highest performance of an ASIP with pipelined architecture under given gate count and power consumption constraints. The problem formalization as well as the proposed algorithm can be considered as an extension of our previous work toward a pipelined architecture. The experimental results show that the proposed method is quite effective and efficient.
- 社団法人電子情報通信学会の論文
- 1995-12-25
著者
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Binh Nguyen
Department Of Information And Computer Sciences Toyohashi University Of Technology
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IMAI Masaharu
Department of Information and Computer Sciences, Toyohashi University of Technology
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SHIOMI Akichika
Department of Information and Computer Sciences, Toyohashi University of Technology
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HIKICHI Nobuyuki
Software Research Associates, Inc.
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Imai M
Graduate School Of Information Science Technology Osaka University
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Imai Masaharu
Department Of Information And Computer Sciences Toyohashi University Of Technology
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Shiomi A
Shizuoka Univ. Hamamatsu‐shi Jpn
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Shiomi Akichika
Department Of Computer Science Faculty Of Information Shizuoka University
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Hikichi Nobuyuki
Software Research Associates Inc.
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Imai Masaharu
Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka Univ
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- Performance Evaluation of STRON: A Hardware Implementation of a Real-Time OS (Special Section on VLSI Design and CAD Algorithms)
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